Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Some high-speed interfaces, such as high-speed communication interfaces for example, are serial interfaces, and some high-speed communication serial interfaces are source synchronous or system synchronous. In source synchronous communication, a transmitter sends a clock signal separate from the data, and a receiver uses this forwarded clock for data reception. In system synchronous communication, a common clock is used by both transmitter and receiver.
However, more recently, high-speed communication serial interfaces are self-synchronous. In self-synchronous communication, a transmitter generates a serial stream of information including both data and clock information. For example, data and clock information may be transmitted together on a single wire, or on a pair of wires using differential signaling. A receiver having a clock data recovery (“CDR”) circuit recovers and separates the data and clock information embedded in the transmitted serial data stream.
Some CDR circuits use a phased-locked loop (“PLL”). Conventionally, such a PLL is implemented to lock to an incoming serial data stream transmitted by a transmitter using a reference clock signal allowing recovery of a clock signal. The recovered clock signal may have a frequency that at least substantially, if not exactly, matches that of the clock signal used by the transmitter to generate the transmitted serial data stream.
Conventionally, a CDR circuit outputs a fixed-width parallel data bus and the recovered clock signal. The CDR circuit may include a serial-to-parallel converter for deserializing the data of the serial data stream received. The recovered clock signal may thus be a factor slower in frequency than the clock signal used by the transmitter to generate the serial data stream transmitted, and this factor may be dependent upon the bit width of the parallel data bus.
Some PLL-based CDR circuits are designed for a frequency range. The bottom of this frequency range for example may be approximately one Giga-bits-per-second (“Gbps”). If a lower frequency than the bottom of a frequency range of a PLL-based CDR is to be used, then conventionally a digital data recovery circuit is coupled on an output side of the PLL-based CDR.
In brief, if the PLL-based CDR is designed to operate at a faster rate than the incoming serial data stream, the incoming serial data stream is oversampled by the PLL-based CDR. A digital data recovery circuit is used to extract “real data bits” from the oversampled bits output on the parallel data bus of the PLL-based CDR. So, for example, if the clock signal used by the transmitter to generate the serial data stream transmitted was 125 Mega-bps (“Mbps”) and the PLL-based CDR was designed to operate at a bottom frequency of one Gbps, then output of the PLL-based CDR would be oversampled by an oversampling factor of eight, namely a real bit would generally be represented by eight oversampled bits.
Generally, digital oversampling involves detecting the location of data transitions and sampling at the midpoint between these transitions. Unfortunately, if a communication channel is too noisy or if a transmission is too attenuated, or a combination thereof, resolving real bits from oversampled bits may be problematic, and conventional transition detection may not be sufficient. Noise or attenuation may introduce “glitches” in an oversampled input stream, where such glitches are detected as real edges or data transitions. Thus, the sampling point in an oversampled input stream may be off. Furthermore, bits may be output as “real” bits even though they are not because erroneous bits caused by glitches are detected as being real bits.
A low-pass filter may be added to a receiver to remove glitches from a received stream; however, such filtering is generally insufficient for the more noisy communication channels. Another alternative is to add a PLL-based CDR designed to a lower frequency range to match that of the transmitter; however, this may add complexity in the form of additional components, as the lower frequency range may be too slow to accommodate higher transmission rates.